High speed circuits forming components of analog to digital converters (ADCs) and digital to analog converters (DACs), including delta-sigma (ΔΣ) modulators, are required to provide ever increasing performance. This involves conflicting attributes such as size, cost, complexity, power, speed, signal bandwidth, noise and stability. Products demanding this increased performance include data and signal transceivers in audio, video, and RF applications.
Approaches to improving the performance of modulators have included employing high order, low-distortion architectures. This involves an increased number of adder inputs and increased coefficients. While increasing the number of adder inputs can obtain more effective modulator feedback, instability can also increase. Furthermore, increasing coefficients can improve the noise transfer function (NTF); however, a result is an adder with a low feedback factor, β. This low β results in high power consumption, contrary to applications' demands.
There are other approaches to adder design that attempt to improve performance. For example, a current mode adder. However, to provide increased bandwidth, this design requires large DC current, again contrary to applications' needs. These trade-offs cause restrictions on the operation speed and circuit density of their devices.
FIG. 1 is a block diagram 100 of a known third-order modulator including a conventional switched-capacitor-based active adder 105, detailed in FIG. 2. As mentioned, as the number of adder inputs and coefficients are increased, the adder feedback factor β becomes lower, hence high power consumption to get wide bandwidth or good phase margin.
In the circuit of FIG. 1, input U 110 is applied to summing nodes 105 and 115. Output of summing node 115 is applied to input of integrator 120. Output of integrator 120 is applied to input of feedforward path 125 and input of summing node 130. Output of summing node 130 is applied to input of integrator 135. Output of integrator 135 is applied to input of feedforward path 140 and input of integrator 145. Output of integrator 145 is applied to input of feedback path 150, whose output is applied to summing node 130. Output of integrator 145 is also applied to summing node 105, whose output is applied to quantizer 155. Quantizer output is returned to summing node 115 by digital output feedback path with DAC 160 and also provides output V 165. Outlined section depicts embedded-adder quantizer 170.
FIG. 2 is a diagram 200 illustrating a conventional switched-capacitor-based active adder detail as from FIG. 1 when the adder is in the addition mode. VIN 205 corresponds to FIG. 1 input U 110, V1st 210 corresponds to FIG. 1 path 125, V2nd 215 corresponds to FIG. 1 path 140, and V3rd 220 corresponds to FIG. 1 output of integrator 145. For single-bit modulators, passive adders can be used before the quantizer, because dynamic range scaling lowers the adder gain. However, multi-bit modulators require active adders to realize the adder gain and to relax the design requirements of the quantizer. For the third-order modulator shown in FIG. 1, the feedback factor of the active adder is only 1/9, even without considering the parasitic input capacitance of the opamp. To reduce the swing and the power consumption of the first integrator, multi-level quantizers which increase the load capacitance of the adder are included. This effect only gets worse for higher-order modulators and higher-resolution quantizers. The bandwidth of the opamp needs to be wide, and hence large power is consumed in the adder.
FIG. 3 is a diagram 300 illustrating a known transconductance (gm)-cell-based current mode adder exhibiting large DC current consumption. Components include current sources 305, VREF current source 310, VIN current source 315, V1st current source 320, V2nd current source 325, and V3rd current source 330.
Each of these approaches involves negative tradeoffs among size, cost, complexity, power, speed, signal bandwidth, noise and stability. What is needed are techniques for improving performance without increasing power consumption or impacting bandwidth.